QuanFINE™ structure is built on the concept of a GaN-SiC hybrid material, that combines the high-electron-velocity thin GaN with the high-breakdown bulk SiC, which has been realized by SweGaN’s revolutionary hot-wall MOCVD process and proven to be competent for the use in both high-frequency and power transistors. For high-frequency applications, QuanFINE™ features a buffer-free HEMT heterostructure, where the AlN nucleation layer serves effectively as a back-side barrier. Therefore, the electrons in the thin GaN channel (< 250 nm) are well confined in the quantum-well–like structure by the front-side and back-side barriers. For power applications, QuanFINE™ utilizes the semi-insulating SiC substrate as the voltage blocking layer, the quality and resistivity of which is significantly higher than the conventional thick carbon-doped GaN buffer layer. Moreover, it also offers the best thermal management in the class, resulting from the nearly perfect GaN–SiC interface. See more via the following link, (

Picture of QuanFINE trademarked image
Picture of QuanFINE trademarked image
AFM images of SweGaN’s AlGaN (left) and InAlN (right) HEMT heterostructures.


Using SweGaN’s proprietary high-mobility growth process, the channel electron mobility > 2000 cm2/V-s and > 1800 cm2/V-s can be achieved in the epiwafers with AlGaN/GaN and InAlN/AlN/GaN heterostructures, respectively, which is 20 to 30% higher than the conventional channel electron mobility. Typically, the channel heterojunction is atomically abrupt. The surface morphology of the HEMT heterostructures exhibit a low roughness of 0.2 nm and contains limited pits/defects. The record-high mobility enables higher efficiency and higher operation frequency of the transistors.


GaN and AlN epitaxial layers grown by SweGaN’s high-temperature process exhibit excellent structural quality. Typically, the threading dislocation density in the GaN layer is in low 108 cm-2 regime and the AlN nucleation layer is free of grain boundaries. This is the best structural quality in the class, which not only guarantees the GaN robustness but also dramatically reduces the risk of device failure due to the structural defects.

TEM image
Cross-sectional TEM image at the interface of GaN/AlN/SiC region.
Picture of layers


The conventional Thermal Boundary Resistance (TBR) in the GaN – SiC interface causes up to 40% additional channel temperature rise in transistors. Using our ultra-low-TBR AlN nucleation layer, we have been able to reduce this additional temperature rise to a negligible level. The outstanding structural quality of the thin AlN nucleation layer significantly improves the heat transport from the channel down to the high-thermal-conductivity SiC substrate. This allows us to address one of the biggest challenges with RF and power devices: reliability. By reducing the operational temperature by 25 °C, the device lifetime is increased by a factor of 10.